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71M6521DE/DH/FE Data Sheet
MSB
LSB
SM
-
SM21
REN1
TB81
RB81
TI1
RI1
Table 16: The S1CON register
Bit
S0CON.7
Symbol
SM0
Function
These two bits set the UART0 mode:
Mode
0
Description
N/A
SM0
0
SM1
0
S0CON.6
SM1
1
2
3
8-bit UART
9-bit UART
9-bit UART
0
1
1
1
0
1
S0CON.5
S0CON.4
S0CON.3
S0CON.2
S0CON.1
S0CON.0
Bit
S1CON.7
SM20
REN0
TB80
RB80
TI0
RI0
Symbol
SM
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9 th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU, depending
on the function it performs (parity check, multiprocessor communication etc.)
In modes 2 and 3 it is the 9 th data bit received. In Mode 1, if SM20 is 0, RB80 is the
stop bit. In mode 0 this bit is not used. Must be cleared by software
Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be
cleared by software.
Receive interrupt flag, set by hardware after completion of a serial reception. Must
be cleared by software
Table 17: The S0CON Bit Functions
Function
Sets the baud rate for UART1
SM
0
1
Mode
A
B
Description
9-bit UART
8-bit UART
Baud Rate
variable
variable
The 9 transmitted data bit in Mode A. Set or cleared by the MPU, depending on the
S1CON.5
S1CON.4
S1CON.3
S1CON.2
S1CON.1
S1CON.0
SM21
REN1
TB81
RB81
TI1
RI1
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
th
function it performs (parity check, multiprocessor communication etc.)
In Modes A and B, it is the 9 th data bit received. In Mode B, if SM21 is 0, RB81 is the
stop bit. Must be cleared by software
Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be
cleared by software.
Receive interrupt flag, set by hardware after completion of a serial reception. Must
be cleared by software
Table 18: The S1CON Bit Functions
Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter
or timer operations.
In timer mode, the register is incremented every machine cycle meaning that it counts up after every 12 periods of the
MPU clock signal.
Rev 3
Page: 25 of 107
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